1. Field of the Invention
The present invention relates to a complementary MOS transistor having a strained Si channel.
2. Description of the Related Art
The advancement of an Si-LSI device has been achieved with the enhancement of the performance of a MOS transistor which is a basic unit of the Si-LSI device. As the performance of the MOS transistor is closely related to the mobility of a carrier (electron, hole) traveling in a channel, attention has been paid to techniques for improving the carrier mobility. One technique for improving the mobility is a strained Si technique. For example, an Si layer is formed on a strain-relaxed SiGe layer to apply tensile strain to Si of a channel in an n-channel MOS transistor, while a gate electrode is coated with a stressor made of a SiN film to improve the electron mobility in a p-channel MOS transistor.
However, in the case of, for example, the method in which the Si layer is formed on the strain-relaxed SiGe layer, the dislocation density of the surface of the relaxed SiGe layer is high, leading to problems such as the increase of a leakage current. Further, in the case of the method which coats with the stressor made of the SiN film, the process of manufacturing an FET is naturally complicated, and the amount of strain changes with the change of the FET in size, so that, for example, redesigning is required to change the thickness of the SiN film to adjust the amount of strain, and there arises a problem that the film comes off if the thickness of the SiN film is too large.
Furthermore, in JP-A 2004-214386 (KOKAI), a crystalline metal oxide insulating film having lattice spacing different from that of a substrate is formed as a gate insulating film on a channel to modulate the lattice spacing of a channel area, such that the mobility of the carrier is improved.
Here, there is concern over the increase of the leakage current when the gate insulating film is polycrystalline. In addition, according to the above-mentioned patent publication, the Si substrate substantially uniformly contains an amount of strain of about 0.7% in an area up to 50 nm from an interface because the gate insulating film is an epitaxial film. When such an amount of strain exists over 50 nm or more, there is concern over the susceptibility to mechanical shocks such that device characteristics might deteriorate due to the relaxation of strain by the occurrence of a dislocation, that is, a crystal defect caused by a small shock. Moreover, the variation between devices increases.
Furthermore, for the manufacture of the n- and p-channel MOS transistors, the gate insulating films made of materials of different kinds have to be used to apply tensile and compressive strain to the channels, so that the process of manufacturing a complementary MOS transistor is extremely complicated.